ecggsr  2.0.0.0
ecggsr.h
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44 // ----------------------------------------------------------------------------
45 
46 #ifndef _ECGGSR_H_
47 #define _ECGGSR_H_
48 
49 #ifdef __cplusplus
50 extern "C"{
51 #endif
52 
53 #include "mikrosdk_version.h"
54 
55 #ifdef __GNUC__
56 #if mikroSDK_GET_VERSION < 20800ul
57 #include "rcu_delays.h"
58 #else
59 #include "delays.h"
60 #endif
61 #endif
62 
63 #include "drv_digital_out.h"
64 #include "drv_digital_in.h"
65 #include "drv_i2c_master.h"
66 
67 // -------------------------------------------------------------- PUBLIC MACROS
68 
89 #define ECGGSR_SLAVE_ADDRESS 0x30
90  // ecggsr_cfg
91 
102 #define ECGGSR_MAP_MIKROBUS( cfg, mikrobus ) \
103  cfg.scl_pin = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
104  cfg.sda_pin = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
105  cfg.enable_pin = MIKROBUS( mikrobus, MIKROBUS_CS );
106 
107  // ecggsr_map
109  // ecggsr
111 
112 
117 #define ECGGSR_RETVAL uint8_t
118 
124 #define ECGGSR_GPIO_SYNC_REG 0x0F
125 #define ECGGSR_LED_CFG_REG 0x10
126 #define ECGGSR_LED_WAIT_LOW_REG 0x11
127 #define ECGGSR_LED1_CURRL_REG 0x12
128 #define ECGGSR_LED1_CURRH_REG 0x13
129 #define ECGGSR_LED2_CURRL_REG 0x14
130 #define ECGGSR_LED2_CURRH_REG 0x15
131 #define ECGGSR_LED3_CURRL_REG 0x16
132 #define ECGGSR_LED3_CURRH_REG 0x17
133 #define ECGGSR_LED4_CURRL_REG 0x18
134 #define ECGGSR_LED4_CURRH_REG 0x19
135 #define ECGGSR_LED12_MODE_REG 0x2C
136 #define ECGGSR_LED34_MODE_REG 0x2D
137 #define ECGGSR_MAN_SEQ_CFG_REG 0x2E
138 #define ECGGSR_PD_CFG_REG 0x1A
139 #define ECGGSR_PDOFFX_LEDOFF_REG 0x1B
140 #define ECGGSR_PDOFFX_LEDON_REG 0x1C
141 #define ECGGSR_PD_AMPRCCFG_REG 0x1D
142 #define ECGGSR_PD_AMPCFG_REG 0x1E
143 #define ECGGSR_OFE1_PD_THCFG_REG 0x1F
144 #define ECGGSR_SEQ_CNT_REG 0x30
145 #define ECGGSR_SEQ_DIV_REG 0x31
146 #define ECGGSR_SEQ_START_REG 0x32
147 #define ECGGSR_SEQ_PER_REG 0x33
148 #define ECGGSR_SEQ_LED_ST_REG 0x34
149 #define ECGGSR_SEQ_LED_STO_REG 0x35
150 #define ECGGSR_SEQ_SECLED_STA_REG 0x36
151 #define ECGGSR_SEQ_SECLED_STO_REG 0x37
152 #define ECGGSR_SEQ_ITG_STA_REG 0x38
153 #define ECGGSR_SEQ_ITG_STO_REG 0x39
154 #define ECGGSR_SEQ_SDP1_STA_REG 0x3A
155 #define ECGGSR_SEQ_SDP1_STO_REG 0x3B
156 #define ECGGSR_SEQ_SDP2_STA_REG 0x3C
157 #define ECGGSR_SEQ_SDP2_STO_REG 0x3D
158 #define ECGGSR_SEQ_SDM1_STA_REG 0x3E
159 #define ECGGSR_SEQ_SDM1_STO_REG 0x3F
160 #define ECGGSR_SEQ_SDM2_STA_REG 0x40
161 #define ECGGSR_SEQ_SDM2_STO_REG 0x41
162 #define ECGGSR_SEQ_ADC_REG 0x42
163 #define ECGGSR_SEQ_ADC2TIA_REG 0x43
164 #define ECGGSR_SEQ_ADC3TIA_REG 0x44
165 #define ECGGSR_SD_SUBS_REG 0x45
166 #define ECGGSR_SEQ_CFG_REG 0x46
167 #define ECGGSR_SEQ_ERR_REG 0x47
168 #define ECGGSR_SEQ_OVS_SEL_REG 0x48
169 #define ECGGSR_SEQ_OVS_VAL_REG 0x49
170 #define ECGGSR_SEQ_DIS_SEL_REG 0x4A
171 #define ECGGSR_SEQ_DIS_VAL1_REG 0x4B
172 #define ECGGSR_SEQ_DIS_VAL2_REG 0x4C
173 #define ECGGSR_CYC_COUNTER_REG 0x60
174 #define ECGGSR_SEQ_COUNTER_REG 0x61
175 #define ECGGSR_SUBS_COUNTER_REG 0x62
176 #define ECGGSR_OFE_CFGA_REG 0x50
177 #define ECGGSR_OFE1_SD_THCFG_REG 0x51
178 #define ECGGSR_OFE_CFGC_REG 0x52
179 #define ECGGSR_OFE_CFGD_REG 0x53
180 #define ECGGSR_OFE1_CFGA_REG 0x54
181 #define ECGGSR_OFE1_CFGB_REG 0x55
182 #define ECGGSR_OFE2_PD_THCFG_REG 0x56
183 #define ECGGSR_OFE2_SD_THCFG_REG 0x57
184 #define ECGGSR_OFE2_CFGA_REG 0x58
185 #define ECGGSR_OFE2_CFGB_REG 0x59
186 #define ECGGSR_LTFDATA0_L_REG 0x20
187 #define ECGGSR_LTFDATA0_H_REG 0x21
188 #define ECGGSR_LTFDATA1_L_REG 0x22
189 #define ECGGSR_LTFDATA1_H_REG 0x23
190 #define ECGGSR_ITIME_REG 0x24
191 #define ECGGSR_LTF_CONFIG_REG 0x25
192 #define ECGGSR_LTF_SEL_REG 0x26
193 #define ECGGSR_LTF_GAIN_REG 0x27
194 #define ECGGSR_LTF_CONTROL_REG 0x28
195 #define ECGGSR_AZ_CONTROL_REG 0x29
196 #define ECGGSR_OFFSET0_REG 0x2A
197 #define ECGGSR_OFFSET1_REG 0x2B
198 #define ECGGSR_LTF_THRESHOLD_LOW0_REG 0x6C
199 #define ECGGSR_LTF_THRESHOLD_LOW1_REG 0x6D
200 #define ECGGSR_LTF_THRESHOLD_HIGH0_REG 0x6E
201 #define ECGGSR_LTF_THRESHOLD_HIGH1_REG 0x6F
202 #define ECGGSR_EAF_CFG_REG 0x70
203 #define ECGGSR_EAF_GST_REG 0x80
204 #define ECGGSR_EAF_BIAS_REG 0x81
205 #define ECGGSR_EAF_DAC_REG 0x82
206 #define ECGGSR_EAF_DAC1_L_REG 0x83
207 #define ECGGSR_EAF_DAC1_H_REG 0x84
208 #define ECGGSR_EAF_DAC2_L_REG 0x85
209 #define ECGGSR_EAF_DAC2_H_REG 0x86
210 #define ECGGSR_EAF_DAC_CFG_REG 0x87
211 #define ECGGSR_OFE_NOTCH_REG 0x5A
212 #define ECGGSR_ECG_MODE_REG 0x5B
213 #define ECGGSR_ECG_CFGA_REG 0x5C
214 #define ECGGSR_ECG_CFGB_REG 0x5D
215 #define ECGGSR_ECG_THRESHOLD_LOW_REG 0x6A
216 #define ECGGSR_ECG_THRESHOLD_HIGH_REG 0x6B
217 #define ECGGSR_ECG_CFGC_REG 0x5E
218 #define ECGGSR_ECG_CFGD_REG 0x5F
219 #define ECGGSR_ADC_THRESHOLD_REG 0x68
220 #define ECGGSR_ADC_THRESHOLD_CFG_REG 0x69
221 #define ECGGSR_ADC_CFGA_REG 0x88
222 #define ECGGSR_ADC_CFGB_REG 0x89
223 #define ECGGSR_ADC_CFGC_REG 0x8A
224 #define ECGGSR_ADC_CHANNEL_MASK_L_REG 0x8B
225 #define ECGGSR_ADC_CHANNEL_MASK_H_REG 0x8C
226 #define ECGGSR_ADC_DATA_L_REG 0x8E
227 #define ECGGSR_ADC_DATA_H_REG 0x8F
228 #define ECGGSR_FIFO_CFG_REG 0x78
229 #define ECGGSR_FIFO_CNTRL_REG 0x79
230 #define ECGGSR_FIFOL_REG 0xFE
231 #define ECGGSR_FIFOH_REG 0xFF
232 #define ECGGSR_CONTROL_REG 0x00
233 #define ECGGSR_GPIO_A_REG 0x08
234 #define ECGGSR_GPIO_E_REG 0x09
235 #define ECGGSR_GPIO_O_REG 0x0A
236 #define ECGGSR_GPIO_I_REG 0x0B
237 #define ECGGSR_GPIO_P_REG 0x0C
238 #define ECGGSR_GPIO_SR_REG 0x0D
239 #define ECGGSR_SUBID_REG 0x91
240 #define ECGGSR_ID_REG 0x92
241 #define ECGGSR_STATUS_REG 0xA0
242 #define ECGGSR_STATUS2_REG 0xA1
243 #define ECGGSR_CLIPSTATUS_REG 0xA2
244 #define ECGGSR_LEDSTATUS_REG 0xA3
245 #define ECGGSR_FIFOSTATUS_REG 0xA4
246 #define ECGGSR_LTFSTATUS_REG 0xA5
247 #define ECGGSR_FIFOLEVEL_REG 0xA6
248 #define ECGGSR_INTENAB_REG 0xA8
249 #define ECGGSR_INTENAB2_REG 0xA9
250 #define ECGGSR_INTR_REG 0xAA
251 #define ECGGSR_INTR2_REG 0xAB
252 
253 #define ECGGSR_DEV_ID_MASK 0xFC
254 #define ECGGSR_DEV_ID 0x54
255 
256 
257 // 35mA current flows through LEDs.
258 #define ECGGSR_LED_CURR_LOW_2 0x80
259 #define ECGGSR_LED_CURR_HIGH_2 0x59
260 
261 
262 // 100mA current flows through LEDs.
263 #define ECGGSR_LED_CURR_LOW_3 0xC0
264 #define ECGGSR_LED_CURR_HIGH_3 0xFF
265 
266 // PPG related definitions.
267 #define ECGGSR_ENABLE_OSC_AND_LDO 0x03
268 #define ECGGSR_READ_VALUE_CONTROL_REG 0x83
269 #define ECGGSR_ENABLE_REF_AND_DIODES 0x8B
270 #define ECGGSR_ENABLE_LED12_OUTPUT 0x99
271 #define ECGGSR_ENABLE_LED4_OUTPUT 0x90
272 #define ECGGSR_CONF_PHOTODIODE 0x3E
273 #define ECGGSR_SUNLIGHT_COMPENSATION 0x5E
274 #define ECGGSR_FEEDBACK_RESISTOR 0xE2
275 #define ECGGSR_ENABLE_PHOTOAMPLIFIER 0xBC
276 #define ECGGSR_START_PPG 0xE1
277 #define ECGGSR_ENABLE_ADC 0x01
278 #define ECGGSR_START_ADC_CONVERSION 0x01
279 #define ECGGSR_ENABLE_OFE_AND_BIAS 0xE6
280 #define ECGGSR_OFE1_CFGA 0x70
281 #define ECGGSR_OFE2_CFGA 0x70
282 #define ECGGSR_ADC_DATA_H_MASK 0x3F
283 #define ECGGSR_PPG_SCALE_VAL 0x64
284 #define ECGGSR_PD_LED_CURRENT 0x80
285 #define ECGGSR_PPG_L_THRESHOLD 0x48
286 #define ECGGSR_PPG_H_THRESHOLD 0x5F
287 #define ECGGSR_PPG_MAX_VAL 0x64
288 
289 // ECG related definitions.
290 #define ECGGSR_ENABLE_SIG_REFERENCE 0x80
291 #define ECGGSR_ENABLE_BIAS_AND_GAIN 0x09
292 #define ECGGSR_INPUT_AND_REF_VOLTAGE 0xB0
293 #define ECGGSR_RESISTIVE_BIASING 0xA0
294 #define ECGGSR_GAIN_SETTINGS_STAGES1_2 0x0B
295 #define ECGGSR_ENABLE_ECG_AMPLIFIER 0x88
296 #define ECGGSR_GAIN_SETTINGS_STAGE3 0x04
297 #define ECGGSR_ENABLE_REF_AMPLIFIER 0x01
298 #define ECGGSR_START_SEQUENCER 0xE1
299 #define ECGGSR_SELECT_EFE 0x40
300 #define ECGGSR_SELECT_AMPLIFIER_INPUT 0x01
301 #define ECGGSR_ECG_SCALE_VAL 0x02
302 
303 // GSR related definitions.
304 #define ECGGSR_ENABLE_GPIO1_ANALOG 0x02
305 #define ECGGSR_SET_SLEW_RATE_GPIO1 0x02
306 #define ECGGSR_SET_GPIO1_AS_INPUT 0x46
307 #define ECGGSR_SET_RES_BIAS_GPIO1 0x40
308 
309  // generic_registers
311  // ecggsr
313 
314 // --------------------------------------------------------------- PUBLIC TYPES
315 
325 typedef enum
326 {
330 
333 
338 typedef struct
339 {
341  i2c_master_t i2c;
342 
344  uint8_t slave_address;
345 
347  pin_name_t enable_pin;
348 
349 } ecggsr_t;
350 
356 typedef struct
357 {
359  pin_name_t scl_pin;
360  pin_name_t sda_pin;
361  pin_name_t enable_pin;
362 
364  uint32_t i2c_speed;
365  uint8_t i2c_address;
366 
369 
370 } ecggsr_cfg_t;
371 
376 typedef enum
377 {
381  // End types group
383 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
384 
397 
405 err_t ecggsr_init( ecggsr_t *ctx, ecggsr_cfg_t* cfg );
406 
414 
423 err_t ecggsr_write_reg( ecggsr_t *ctx, uint8_t register_address, uint8_t transfer_data );
424 
434 err_t ecggsr_read_reg( ecggsr_t *ctx, uint8_t register_address, uint8_t *data_out, uint8_t num_of_regs );
435 
442 void ecggsr_read_dev_id( ecggsr_t *ctx, uint8_t *dev_id_out );
443 
449 void ecggsr_reset( ecggsr_t *ctx );
450  // End public_function group
452 
453 #ifdef __cplusplus
454 }
455 #endif
456 
457 #endif // _ECGGSR_H_
458 // ------------------------------------------------------------------------- END
ecggsr_reset
void ecggsr_reset(ecggsr_t *ctx)
ECG GSR Reset function.
ecggsr_default_cfg
void ecggsr_default_cfg(ecggsr_t *ctx, ecggsr_cfg_t *cfg)
Click Default Configuration function.
ecggsr_cfg_t::i2c_address
uint8_t i2c_address
Definition: ecggsr.h:365
ecggsr_t::i2c
i2c_master_t i2c
Definition: ecggsr.h:341
ENABLE_OXIMETER_FUNCTIONALITY
@ ENABLE_OXIMETER_FUNCTIONALITY
Definition: ecggsr.h:327
ENABLE_HEARTRATE_FUNCTIONALITY
@ ENABLE_HEARTRATE_FUNCTIONALITY
Definition: ecggsr.h:328
ecggsr_t
Context structure.
Definition: ecggsr.h:339
ecggsr_cfg_t::scl_pin
pin_name_t scl_pin
Definition: ecggsr.h:359
ecggsr_init_error
@ ecggsr_init_error
Definition: ecggsr.h:379
ecggsr_cfg_t::click_functionality
ecggsr_functionality_t click_functionality
Definition: ecggsr.h:368
ENABLE_GALVANIC_SKIN_RESPONSE_FUNCTIONALITY
@ ENABLE_GALVANIC_SKIN_RESPONSE_FUNCTIONALITY
Definition: ecggsr.h:329
DEFAULT_ECGGSR_CLICK_FUNCTIONALITY
@ DEFAULT_ECGGSR_CLICK_FUNCTIONALITY
Definition: ecggsr.h:331
ecggsr_functionality_t
ecggsr_functionality_t
ECG GSR type of measurement selector.
Definition: ecggsr.h:326
ecggsr_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: ecggsr.h:364
ecggsr_cfg_t
Configuration structure.
Definition: ecggsr.h:357
ecggsr_t::enable_pin
pin_name_t enable_pin
Definition: ecggsr.h:347
ecggsr_write_reg
err_t ecggsr_write_reg(ecggsr_t *ctx, uint8_t register_address, uint8_t transfer_data)
Generic Write function.
ecggsr_cfg_setup
void ecggsr_cfg_setup(ecggsr_cfg_t *cfg)
ECG GSR configuration object setup function.
ecggsr_init
err_t ecggsr_init(ecggsr_t *ctx, ecggsr_cfg_t *cfg)
Initialization function.
ecggsr_err_t
ecggsr_err_t
Error Code.
Definition: ecggsr.h:377
ecggsr_cfg_t::enable_pin
pin_name_t enable_pin
Definition: ecggsr.h:361
ecggsr_read_reg
err_t ecggsr_read_reg(ecggsr_t *ctx, uint8_t register_address, uint8_t *data_out, uint8_t num_of_regs)
Generic Read function.
ecggsr_ok
@ ecggsr_ok
Definition: ecggsr.h:378
ecggsr_read_dev_id
void ecggsr_read_dev_id(ecggsr_t *ctx, uint8_t *dev_id_out)
ECG GSR Read ID function.
ecggsr_t::slave_address
uint8_t slave_address
Definition: ecggsr.h:344
ecggsr_cfg_t::sda_pin
pin_name_t sda_pin
Definition: ecggsr.h:360