isoadc7
2.1.0.0
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Settings for registers of ISO ADC 7 Click driver. More...
Settings for registers of ISO ADC 7 Click driver.
#define ISOADC7_CFG_GC_DLY_1024 0x1200 |
#define ISOADC7_CFG_GC_DLY_128 0x0C00 |
#define ISOADC7_CFG_GC_DLY_16 0x0600 |
#define ISOADC7_CFG_GC_DLY_16384 0x1A00 |
#define ISOADC7_CFG_GC_DLY_2 0x0000 |
#define ISOADC7_CFG_GC_DLY_2048 0x1400 |
#define ISOADC7_CFG_GC_DLY_256 0x0E00 |
#define ISOADC7_CFG_GC_DLY_32 0x0800 |
#define ISOADC7_CFG_GC_DLY_32768 0x1C00 |
#define ISOADC7_CFG_GC_DLY_4 0x0200 |
#define ISOADC7_CFG_GC_DLY_4096 0x1600 |
#define ISOADC7_CFG_GC_DLY_512 0x1000 |
#define ISOADC7_CFG_GC_DLY_64 0x0A00 |
#define ISOADC7_CFG_GC_DLY_65536 0x1E00 |
#define ISOADC7_CFG_GC_DLY_8 0x0400 |
#define ISOADC7_CFG_GC_DLY_8192 0x1800 |
#define ISOADC7_CFG_GC_DLY_MASK 0x1E00 |
#define ISOADC7_CFG_GC_EN 0x0100 |
#define ISOADC7_CFG_GPO_DAT_ONE 0x2000 |
#define ISOADC7_CFG_GPO_EN 0x4000 |
ISO ADC 7 CFG register setting.
Specified setting for CFG register of ISO ADC 7 Click driver.
#define ISOADC7_CH0_CFG_MUX_AC_DIAG 0x0003 |
#define ISOADC7_CH0_CFG_MUX_AIN0_DISCON 0x0001 |
#define ISOADC7_CH0_CFG_MUX_AIN0P_AIN0N 0x0000 |
#define ISOADC7_CH0_CFG_MUX_DC_DIAG 0x0002 |
#define ISOADC7_CH0_CFG_MUX_MASK 0x0003 |
#define ISOADC7_CH0_CFG_PHASE_MASK 0xFFC0 |
ISO ADC 7 CH0_CFG register setting.
Specified setting for CH0_CFG register of ISO ADC 7 Click driver.
#define ISOADC7_CH1_CFG_MUX_AC_DIAG 0x0003 |
#define ISOADC7_CH1_CFG_MUX_AIN1_DISCON 0x0001 |
#define ISOADC7_CH1_CFG_MUX_AIN1P_AIN12N 0x0000 |
#define ISOADC7_CH1_CFG_MUX_DC_DIAG 0x0002 |
#define ISOADC7_CH1_CFG_MUX_MASK 0x0003 |
#define ISOADC7_CH1_CFG_PHASE_MASK 0xFFC0 |
ISO ADC 7 CH1_CFG register setting.
Specified setting for CH1_CFG register of ISO ADC 7 Click driver.
#define ISOADC7_CH2_CFG_MUX_AC_DIAG 0x0003 |
#define ISOADC7_CH2_CFG_MUX_AIN2_DISCON 0x0001 |
#define ISOADC7_CH2_CFG_MUX_AIN2P_AIN12N 0x0000 |
#define ISOADC7_CH2_CFG_MUX_DC_DIAG 0x0002 |
#define ISOADC7_CH2_CFG_MUX_MASK 0x0003 |
#define ISOADC7_CH2_CFG_PHASE_MASK 0xFFC0 |
ISO ADC 7 CH2_CFG register setting.
Specified setting for CH2_CFG register of ISO ADC 7 Click driver.
#define ISOADC7_CH2_CFG_TS_CHOP_INV 0x0004 |
#define ISOADC7_CH2_CFG_TS_EN 0x0010 |
#define ISOADC7_CH2_CFG_TS_SEL_EXT 0x0020 |
#define ISOADC7_CH2_CFG_TS_SEL_INT 0x0000 |
#define ISOADC7_CH2_CFG_TS_SEL_MASK 0x0020 |
#define ISOADC7_CLOCK_CH0_EN 0x0100 |
#define ISOADC7_CLOCK_CH1_EN 0x0200 |
#define ISOADC7_CLOCK_CH2_EN 0x0400 |
ISO ADC 7 CLOCK register setting.
Specified setting for CLOCK register of ISO ADC 7 Click driver.
#define ISOADC7_CLOCK_CLK_DIV_12 0x00C0 |
#define ISOADC7_CLOCK_CLK_DIV_2 0x0000 |
#define ISOADC7_CLOCK_CLK_DIV_4 0x0040 |
#define ISOADC7_CLOCK_CLK_DIV_8 0x0080 |
#define ISOADC7_CLOCK_CLK_DIV_MASK 0x00C0 |
#define ISOADC7_CLOCK_OSR_1024 0x000C |
#define ISOADC7_CLOCK_OSR_128 0x0000 |
#define ISOADC7_CLOCK_OSR_16384 0x001C |
#define ISOADC7_CLOCK_OSR_2048 0x0010 |
#define ISOADC7_CLOCK_OSR_256 0x0004 |
#define ISOADC7_CLOCK_OSR_4096 0x0014 |
#define ISOADC7_CLOCK_OSR_512 0x0008 |
#define ISOADC7_CLOCK_OSR_8192 0x0018 |
#define ISOADC7_CLOCK_OSR_MASK 0x001C |
#define ISOADC7_CLOCK_PWR_HIGH 0x0002 |
#define ISOADC7_CLOCK_PWR_LOW 0x0001 |
#define ISOADC7_CLOCK_PWR_MASK 0x0003 |
#define ISOADC7_CLOCK_TURBO_EN 0x0020 |
#define ISOADC7_DCDC_CTRL_DCDC_EN 0x0001 |
#define ISOADC7_DCDC_CTRL_FREQ_1_40_TO_1_53 0x0F00 |
#define ISOADC7_DCDC_CTRL_FREQ_1_50_TO_1_63 0x0E00 |
#define ISOADC7_DCDC_CTRL_FREQ_1_60_TO_1_74 0x0D00 |
#define ISOADC7_DCDC_CTRL_FREQ_1_71_TO_1_86 0x0C00 |
#define ISOADC7_DCDC_CTRL_FREQ_1_82_TO_1_99 0x0B00 |
#define ISOADC7_DCDC_CTRL_FREQ_1_95_TO_2_12 0x0A00 |
#define ISOADC7_DCDC_CTRL_FREQ_2_08_TO_2_27 0x0900 |
#define ISOADC7_DCDC_CTRL_FREQ_2_22_TO_2_42 0x0800 |
#define ISOADC7_DCDC_CTRL_FREQ_2_37_TO_2_59 0x0700 |
#define ISOADC7_DCDC_CTRL_FREQ_2_53_TO_2_76 0x0600 |
#define ISOADC7_DCDC_CTRL_FREQ_2_71_TO_2_95 0x0500 |
#define ISOADC7_DCDC_CTRL_FREQ_2_89_TO_3_15 0x0400 |
#define ISOADC7_DCDC_CTRL_FREQ_3_09_TO_3_36 0x0300 |
#define ISOADC7_DCDC_CTRL_FREQ_3_30_TO_3_59 0x0200 |
#define ISOADC7_DCDC_CTRL_FREQ_3_52_TO_3_84 0x0100 |
#define ISOADC7_DCDC_CTRL_FREQ_3_78_TO_4_10 0x0000 |
ISO ADC 7 DCDC_CTRL register setting.
Specified setting for DCDC_CTRL register of ISO ADC 7 Click driver.
#define ISOADC7_DEVICE_ID 0x2300 |
ISO ADC 7 ID register setting.
Specified setting for ID register of ISO ADC 7 Click driver.
#define ISOADC7_DEVICE_ID_MASK 0xFF00 |
#define ISOADC7_GAIN_1 0x00 |
ISO ADC 7 GAIN setting.
Specified setting for GAIN of ISO ADC 7 Click driver.
#define ISOADC7_GAIN_128 0x07 |
#define ISOADC7_GAIN_16 0x04 |
#define ISOADC7_GAIN_2 0x01 |
#define ISOADC7_GAIN_32 0x05 |
#define ISOADC7_GAIN_4 0x02 |
#define ISOADC7_GAIN_64 0x06 |
#define ISOADC7_GAIN_8 0x03 |
#define ISOADC7_INTERNAL_VREF_MV 1200.0f |
ISO ADC 7 VREF setting.
Specified setting for VREF of ISO ADC 7 Click driver.
#define ISOADC7_MODE_CRC_TYPE_ANSI 0x0800 |
#define ISOADC7_MODE_CRC_TYPE_CCITT 0x0000 |
#define ISOADC7_MODE_CRC_TYPE_MASK 0x0800 |
#define ISOADC7_MODE_DRDY_FMT 0x0001 |
#define ISOADC7_MODE_DRDY_HIZ 0x0002 |
#define ISOADC7_MODE_DRDY_SEL_LOGIC_OR 0x0004 |
#define ISOADC7_MODE_DRDY_SEL_MASK 0x000C |
#define ISOADC7_MODE_DRDY_SEL_MOST_LAGGING 0x0000 |
#define ISOADC7_MODE_DRDY_SEL_MOST_LEADING 0x0008 |
#define ISOADC7_MODE_REG_CRC_EN 0x2000 |
ISO ADC 7 MODE register setting.
Specified setting for MODE register of ISO ADC 7 Click driver.
#define ISOADC7_MODE_RESET 0x0400 |
#define ISOADC7_MODE_RX_CRC_EN 0x1000 |
#define ISOADC7_MODE_TIMEOUT_ENABLE 0x0010 |
#define ISOADC7_MODE_WLENGTH_16BIT 0x0000 |
#define ISOADC7_MODE_WLENGTH_24BIT 0x0100 |
#define ISOADC7_MODE_WLENGTH_32BIT_MSB 0x0300 |
#define ISOADC7_MODE_WLENGTH_32BIT_ZERO 0x0200 |
#define ISOADC7_MODE_WLENGTH_MASK 0x0300 |
#define ISOADC7_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
#define ISOADC7_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
#define ISOADC7_STATUS_CRC_ERR 0x1000 |
#define ISOADC7_STATUS_CRC_TYPE_ANSI 0x0800 |
#define ISOADC7_STATUS_CRC_TYPE_CCITT 0x0000 |
#define ISOADC7_STATUS_CRC_TYPE_MASK 0x0800 |
#define ISOADC7_STATUS_DRDY0 0x0001 |
#define ISOADC7_STATUS_DRDY1 0x0002 |
#define ISOADC7_STATUS_DRDY2 0x0004 |
#define ISOADC7_STATUS_F_RESYNC 0x4000 |
#define ISOADC7_STATUS_FUSE_FAIL 0x0080 |
#define ISOADC7_STATUS_LOCK 0x8000 |
ISO ADC 7 STATUS register setting.
Specified setting for STATUS register of ISO ADC 7 Click driver.
#define ISOADC7_STATUS_REG_MAP 0x2000 |
#define ISOADC7_STATUS_RESET 0x0400 |
#define ISOADC7_STATUS_SEC_FAIL 0x0040 |
#define ISOADC7_STATUS_WLENGTH_16BIT 0x0000 |
#define ISOADC7_STATUS_WLENGTH_24BIT 0x0100 |
#define ISOADC7_STATUS_WLENGTH_32BIT_MSB 0x0300 |
#define ISOADC7_STATUS_WLENGTH_32BIT_ZERO 0x0200 |
#define ISOADC7_STATUS_WLENGTH_MASK 0x0300 |