digiio
2.1.0.0
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Settings for registers of DIGI IO Click driver. More...
Settings for registers of DIGI IO Click driver.
#define DIGIIO_CONFIG_1_FFILTER_EN_MASK 0x10 |
#define DIGIIO_CONFIG_1_FFILTER_EN_OFF 0x00 |
#define DIGIIO_CONFIG_1_FFILTER_EN_ON 0x10 |
#define DIGIIO_CONFIG_1_FILTER_LONG_4_MS 0x00 |
#define DIGIIO_CONFIG_1_FILTER_LONG_8_MS 0x20 |
#define DIGIIO_CONFIG_1_FILTER_LONG_MASK 0x20 |
#define DIGIIO_CONFIG_1_FLATCH_EN_MASK 0x40 |
#define DIGIIO_CONFIG_1_FLATCH_EN_OFF 0x00 |
#define DIGIIO_CONFIG_1_FLATCH_EN_ON 0x40 |
#define DIGIIO_CONFIG_1_FLED_SET_DOI 0x00 |
#define DIGIIO_CONFIG_1_FLED_SET_MASK 0x01 |
#define DIGIIO_CONFIG_1_FLED_SET_REG 0x01 |
#define DIGIIO_CONFIG_1_FLED_STRETCH_1_S 0x04 |
#define DIGIIO_CONFIG_1_FLED_STRETCH_2_S 0x08 |
#define DIGIIO_CONFIG_1_FLED_STRETCH_3_S 0x0C |
#define DIGIIO_CONFIG_1_FLED_STRETCH_MASK 0x0C |
#define DIGIIO_CONFIG_1_FLED_STRETCH_OFF 0x00 |
#define DIGIIO_CONFIG_1_LED_CURR_LIM_MASK 0x80 |
#define DIGIIO_CONFIG_1_LED_CURR_LIM_OFF 0x00 |
DIGI IO CONFIG_1 register setting.
Specified setting for CONFIG_1 register of DIGI IO Click driver.
#define DIGIIO_CONFIG_1_LED_CURR_LIM_ON 0x80 |
#define DIGIIO_CONFIG_1_SLED_SET_DOI 0x00 |
#define DIGIIO_CONFIG_1_SLED_SET_MASK 0x02 |
#define DIGIIO_CONFIG_1_SLED_SET_REG 0x02 |
#define DIGIIO_CONFIG_2_OW_OFF_C_S_100_UA 0x10 |
#define DIGIIO_CONFIG_2_OW_OFF_C_S_300_UA 0x20 |
#define DIGIIO_CONFIG_2_OW_OFF_C_S_600_UA 0x30 |
#define DIGIIO_CONFIG_2_OW_OFF_C_S_60_UA 0x00 |
#define DIGIIO_CONFIG_2_OW_OFF_C_S_MASK 0x30 |
#define DIGIIO_CONFIG_2_SHT_VDD_THR_10_V 0x04 |
#define DIGIIO_CONFIG_2_SHT_VDD_THR_12_V 0x08 |
#define DIGIIO_CONFIG_2_SHT_VDD_THR_14_V 0x0C |
#define DIGIIO_CONFIG_2_SHT_VDD_THR_9_V 0x00 |
#define DIGIIO_CONFIG_2_SHT_VDD_THR_MASK 0x0C |
#define DIGIIO_CONFIG_2_SYNCH_WD_EN_MASK 0x02 |
#define DIGIIO_CONFIG_2_SYNCH_WD_EN_OFF 0x00 |
#define DIGIIO_CONFIG_2_SYNCH_WD_EN_ON 0x02 |
#define DIGIIO_CONFIG_2_VDD_ON_THR_MASK 0x01 |
#define DIGIIO_CONFIG_2_VDD_ON_THR_OFF 0x00 |
#define DIGIIO_CONFIG_2_VDD_ON_THR_ON 0x01 |
#define DIGIIO_CONFIG_2_WDTO_1200_MS 0xC0 |
#define DIGIIO_CONFIG_2_WDTO_200_MS 0x40 |
#define DIGIIO_CONFIG_2_WDTO_600_MS 0x80 |
#define DIGIIO_CONFIG_2_WDTO_MASK 0xC0 |
#define DIGIIO_CONFIG_2_WDTO_OFF 0x00 |
DIGI IO CONFIG_2 register setting.
Specified setting for CONFIG_2 register of DIGI IO Click driver.
#define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_MASK 0x08 |
#define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_OFF 0x00 |
#define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_ON 0x08 |
#define DIGIIO_CONFIG_DI_OVL_BLANK_300_MS 0x03 |
#define DIGIIO_CONFIG_DI_OVL_BLANK_50_MS 0x02 |
#define DIGIIO_CONFIG_DI_OVL_BLANK_8_MS 0x01 |
#define DIGIIO_CONFIG_DI_OVL_BLANK_MASK 0x03 |
#define DIGIIO_CONFIG_DI_OVL_BLANK_OFF 0x00 |
#define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_MASK 0x04 |
#define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_OFF 0x00 |
#define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_ON 0x04 |
#define DIGIIO_CONFIG_DI_TYP_2_DI_MASK 0x80 |
#define DIGIIO_CONFIG_DI_TYP_2_DI_TYPE_1_3 0x00 |
DIGI IO CONFIG_DI register setting.
Specified setting for CONFIG_DI register of DIGI IO Click driver.
#define DIGIIO_CONFIG_DI_TYP_2_DI_TYPE_2 0x80 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_MASK 0x20 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_OFF 0x00 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_ON 0x20 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_DOI 0x00 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_MASK 0x10 |
#define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_VDDOK 0x10 |
#define DIGIIO_CONFIG_DO_MODE1_ACTIVE_CLAMP_PP 0x02 |
#define DIGIIO_CONFIG_DO_MODE1_HIGH_SIDE 0x00 |
#define DIGIIO_CONFIG_DO_MODE1_HIGH_SIDE_2X 0x01 |
#define DIGIIO_CONFIG_DO_MODE1_MASK 0x03 |
#define DIGIIO_CONFIG_DO_MODE1_SIMPLE_PP 0x03 |
#define DIGIIO_CONFIG_DO_MODE2_ACTIVE_CLAMP_PP 0x08 |
#define DIGIIO_CONFIG_DO_MODE2_HIGH_SIDE 0x00 |
#define DIGIIO_CONFIG_DO_MODE2_HIGH_SIDE_2X 0x04 |
#define DIGIIO_CONFIG_DO_MODE2_MASK 0x0C |
#define DIGIIO_CONFIG_DO_MODE2_SIMPLE_PP 0x0C |
#define DIGIIO_CONFIG_DO_MODE3_ACTIVE_CLAMP_PP 0x20 |
#define DIGIIO_CONFIG_DO_MODE3_HIGH_SIDE 0x00 |
#define DIGIIO_CONFIG_DO_MODE3_HIGH_SIDE_2X 0x10 |
#define DIGIIO_CONFIG_DO_MODE3_MASK 0x30 |
#define DIGIIO_CONFIG_DO_MODE3_SIMPLE_PP 0x30 |
#define DIGIIO_CONFIG_DO_MODE4_ACTIVE_CLAMP_PP 0x80 |
#define DIGIIO_CONFIG_DO_MODE4_HIGH_SIDE 0x00 |
DIGI IO CONFIG_DO register setting.
Specified setting for CONFIG_DO register of DIGI IO Click driver.
#define DIGIIO_CONFIG_DO_MODE4_HIGH_SIDE_2X 0x40 |
#define DIGIIO_CONFIG_DO_MODE4_MASK 0xC0 |
#define DIGIIO_CONFIG_DO_MODE4_SIMPLE_PP 0xC0 |
#define DIGIIO_CRC_DISABLED 0x00 |
#define DIGIIO_CRC_ENABLED 0x01 |
DIGI IO CRC Settings setting.
Specified setting for CRC Settings of DIGI IO Click driver.
#define DIGIIO_CURR_LIM_CL1_1200_MA 0x03 |
#define DIGIIO_CURR_LIM_CL1_130_MA 0x01 |
#define DIGIIO_CURR_LIM_CL1_300_MA 0x02 |
#define DIGIIO_CURR_LIM_CL1_600_MA 0x00 |
#define DIGIIO_CURR_LIM_CL1_MASK 0x03 |
#define DIGIIO_CURR_LIM_CL2_1200_MA 0x0C |
#define DIGIIO_CURR_LIM_CL2_130_MA 0x04 |
#define DIGIIO_CURR_LIM_CL2_300_MA 0x08 |
#define DIGIIO_CURR_LIM_CL2_600_MA 0x00 |
#define DIGIIO_CURR_LIM_CL2_MASK 0x0C |
#define DIGIIO_CURR_LIM_CL3_1200_MA 0x30 |
#define DIGIIO_CURR_LIM_CL3_130_MA 0x10 |
#define DIGIIO_CURR_LIM_CL3_300_MA 0x20 |
#define DIGIIO_CURR_LIM_CL3_600_MA 0x00 |
#define DIGIIO_CURR_LIM_CL3_MASK 0x30 |
#define DIGIIO_CURR_LIM_CL4_1200_MA 0xC0 |
#define DIGIIO_CURR_LIM_CL4_130_MA 0x40 |
#define DIGIIO_CURR_LIM_CL4_300_MA 0x80 |
#define DIGIIO_CURR_LIM_CL4_600_MA 0x00 |
DIGI IO CURR_LIM register setting.
Specified setting for CURR_LIM register of DIGI IO Click driver.
#define DIGIIO_CURR_LIM_CL4_MASK 0xC0 |
#define DIGIIO_DEVICE_ADDRESS_0 0x00 |
DIGI IO chip address setting.
Specified setting for chip address of DIGI IO Click driver.
#define DIGIIO_DEVICE_ADDRESS_1 0x40 |
#define DIGIIO_DEVICE_ADDRESS_2 0x80 |
#define DIGIIO_DEVICE_ADDRESS_3 0xC0 |
#define DIGIIO_DOI_LEVEL_DOI1 0x01 |
#define DIGIIO_DOI_LEVEL_DOI2 0x02 |
#define DIGIIO_DOI_LEVEL_DOI3 0x04 |
#define DIGIIO_DOI_LEVEL_DOI4 0x08 |
#define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F1 0x10 |
#define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F2 0x20 |
#define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F3 0x40 |
#define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F4 0x80 |
DIGI IO DOI_LEVEL register setting.
Specified setting for DOI_LEVEL register of DIGI IO Click driver.
#define DIGIIO_GLOBAL_ERR_LOSS_GND 0x40 |
#define DIGIIO_GLOBAL_ERR_THRM_SHUTD 0x20 |
#define DIGIIO_GLOBAL_ERR_V5_UVLO 0x02 |
#define DIGIIO_GLOBAL_ERR_VDD_LOW 0x04 |
#define DIGIIO_GLOBAL_ERR_VDD_UVLO 0x10 |
#define DIGIIO_GLOBAL_ERR_VDD_WARN 0x08 |
#define DIGIIO_GLOBAL_ERR_VINT_UV 0x01 |
#define DIGIIO_GLOBAL_ERR_W_DOG_ERR 0x80 |
DIGI IO GLOBAL_ERR register setting.
Specified setting for GLOBAL_ERR register of DIGI IO Click driver.
#define DIGIIO_INTERRUPT_ABOVE_VDD_FAULT 0x08 |
#define DIGIIO_INTERRUPT_COMM_ERR 0x80 |
DIGI IO INTERRUPT register setting.
Specified setting for INTERRUPT register of DIGI IO Click driver.
#define DIGIIO_INTERRUPT_CURR_LIM 0x02 |
#define DIGIIO_INTERRUPT_DEMAG_FAULT 0x20 |
#define DIGIIO_INTERRUPT_OVER_LD_FAULT 0x01 |
#define DIGIIO_INTERRUPT_OW_OFF_FAULT 0x04 |
#define DIGIIO_INTERRUPT_SHT_VDD_FAULT 0x10 |
#define DIGIIO_INTERRUPT_SUPPLY_ERR 0x40 |
#define DIGIIO_MASK_ABOVE_VDD_M 0x08 |
#define DIGIIO_MASK_COMM_ERR_M 0x80 |
DIGI IO MASK register setting.
Specified setting for MASK register of DIGI IO Click driver.
#define DIGIIO_MASK_CURR_LIM_M 0x02 |
#define DIGIIO_MASK_OVER_LD_M 0x01 |
#define DIGIIO_MASK_OW_OFF_M 0x04 |
#define DIGIIO_MASK_SHT_VDD_M 0x10 |
#define DIGIIO_MASK_SUPPLY_ERR_M 0x40 |
#define DIGIIO_MASK_VDD_OK_M 0x20 |
#define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD1 0x10 |
#define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD2 0x20 |
#define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD3 0x40 |
#define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD4 0x80 |
DIGI IO OPN_WIR_CH_F register setting.
Specified setting for OPN_WIR_CH_F register of DIGI IO Click driver.
#define DIGIIO_OPN_WIR_CH_F_OW_OFF1 0x01 |
#define DIGIIO_OPN_WIR_CH_F_OW_OFF2 0x02 |
#define DIGIIO_OPN_WIR_CH_F_OW_OFF3 0x04 |
#define DIGIIO_OPN_WIR_CH_F_OW_OFF4 0x08 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN1_MASK 0x10 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN1_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN1_ON 0x10 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN2_MASK 0x20 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN2_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN2_ON 0x20 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN3_MASK 0x40 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN3_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN3_ON 0x40 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN4_MASK 0x80 |
#define DIGIIO_OPN_WR_EN_G_DRV_EN4_OFF 0x00 |
DIGI IO OPN_WR_EN register setting.
Specified setting for OPN_WR_EN register of DIGI IO Click driver.
#define DIGIIO_OPN_WR_EN_G_DRV_EN4_ON 0x80 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN1_MASK 0x01 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN1_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN1_ON 0x01 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN2_MASK 0x02 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN2_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN2_ON 0x02 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN3_MASK 0x04 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN3_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN3_ON 0x04 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN4_MASK 0x08 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN4_OFF 0x00 |
#define DIGIIO_OPN_WR_EN_OW_OFF_EN4_ON 0x08 |
#define DIGIIO_OVR_LD_CH_F_CL1 0x10 |
#define DIGIIO_OVR_LD_CH_F_CL2 0x20 |
#define DIGIIO_OVR_LD_CH_F_CL3 0x40 |
#define DIGIIO_OVR_LD_CH_F_CL4 0x80 |
DIGI IO OVR_LD_CH_F register setting.
Specified setting for OVR_LD_CH_F register of DIGI IO Click driver.
#define DIGIIO_OVR_LD_CH_F_OVL1 0x01 |
#define DIGIIO_OVR_LD_CH_F_OVL2 0x02 |
#define DIGIIO_OVR_LD_CH_F_OVL3 0x04 |
#define DIGIIO_OVR_LD_CH_F_OVL4 0x08 |
#define DIGIIO_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
#define DIGIIO_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
#define DIGIIO_SET_LED_FLED1_MASK 0x01 |
#define DIGIIO_SET_LED_FLED1_OFF 0x00 |
#define DIGIIO_SET_LED_FLED1_ON 0x01 |
#define DIGIIO_SET_LED_FLED2_MASK 0x02 |
#define DIGIIO_SET_LED_FLED2_OFF 0x00 |
#define DIGIIO_SET_LED_FLED2_ON 0x02 |
#define DIGIIO_SET_LED_FLED3_MASK 0x04 |
#define DIGIIO_SET_LED_FLED3_OFF 0x00 |
#define DIGIIO_SET_LED_FLED3_ON 0x04 |
#define DIGIIO_SET_LED_FLED4_MASK 0x08 |
#define DIGIIO_SET_LED_FLED4_OFF 0x00 |
#define DIGIIO_SET_LED_FLED4_ON 0x08 |
#define DIGIIO_SET_LED_SLED1_MASK 0x10 |
#define DIGIIO_SET_LED_SLED1_OFF 0x00 |
#define DIGIIO_SET_LED_SLED1_ON 0x10 |
#define DIGIIO_SET_LED_SLED2_MASK 0x20 |
#define DIGIIO_SET_LED_SLED2_OFF 0x00 |
#define DIGIIO_SET_LED_SLED2_ON 0x20 |
#define DIGIIO_SET_LED_SLED3_MASK 0x40 |
#define DIGIIO_SET_LED_SLED3_OFF 0x00 |
#define DIGIIO_SET_LED_SLED3_ON 0x40 |
#define DIGIIO_SET_LED_SLED4_MASK 0x80 |
#define DIGIIO_SET_LED_SLED4_OFF 0x00 |
DIGI IO SET_LED register setting.
Specified setting for SET_LED register of DIGI IO Click driver.
#define DIGIIO_SET_LED_SLED4_ON 0x80 |
#define DIGIIO_SET_OUT_HIGH_O1_HIGH 0x01 |
#define DIGIIO_SET_OUT_HIGH_O1_LOW 0x00 |
#define DIGIIO_SET_OUT_HIGH_O1_MASK 0x01 |
#define DIGIIO_SET_OUT_HIGH_O2_HIGH 0x02 |
#define DIGIIO_SET_OUT_HIGH_O2_LOW 0x00 |
#define DIGIIO_SET_OUT_HIGH_O2_MASK 0x02 |
#define DIGIIO_SET_OUT_HIGH_O3_HIGH 0x04 |
#define DIGIIO_SET_OUT_HIGH_O3_LOW 0x00 |
#define DIGIIO_SET_OUT_HIGH_O3_MASK 0x04 |
#define DIGIIO_SET_OUT_HIGH_O4_HIGH 0x08 |
#define DIGIIO_SET_OUT_HIGH_O4_LOW 0x00 |
#define DIGIIO_SET_OUT_HIGH_O4_MASK 0x08 |
#define DIGIIO_SET_OUT_SET_DI1_INPUT 0x10 |
#define DIGIIO_SET_OUT_SET_DI1_MASK 0x10 |
#define DIGIIO_SET_OUT_SET_DI1_OUTPUT 0x00 |
#define DIGIIO_SET_OUT_SET_DI2_INPUT 0x20 |
#define DIGIIO_SET_OUT_SET_DI2_MASK 0x20 |
#define DIGIIO_SET_OUT_SET_DI2_OUTPUT 0x00 |
#define DIGIIO_SET_OUT_SET_DI3_INPUT 0x40 |
#define DIGIIO_SET_OUT_SET_DI3_MASK 0x40 |
#define DIGIIO_SET_OUT_SET_DI3_OUTPUT 0x00 |
#define DIGIIO_SET_OUT_SET_DI4_INPUT 0x80 |
#define DIGIIO_SET_OUT_SET_DI4_MASK 0x80 |
#define DIGIIO_SET_OUT_SET_DI4_OUTPUT 0x00 |
DIGI IO SET_OUT register setting.
Specified setting for SET_OUT register of DIGI IO Click driver.
#define DIGIIO_SHT_VDD_CH_F_SH_VDD1 0x01 |
#define DIGIIO_SHT_VDD_CH_F_SH_VDD2 0x02 |
#define DIGIIO_SHT_VDD_CH_F_SH_VDD3 0x04 |
#define DIGIIO_SHT_VDD_CH_F_SH_VDD4 0x08 |
#define DIGIIO_SHT_VDD_CH_F_VDD_OV1 0x10 |
#define DIGIIO_SHT_VDD_CH_F_VDD_OV2 0x20 |
#define DIGIIO_SHT_VDD_CH_F_VDD_OV3 0x40 |
#define DIGIIO_SHT_VDD_CH_F_VDD_OV4 0x80 |
DIGI IO SHT_VDD_CH_F register setting.
Specified setting for SHT_VDD_CH_F register of DIGI IO Click driver.
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_MASK 0x01 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_ON 0x01 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_MASK 0x02 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_ON 0x02 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_MASK 0x04 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_ON 0x04 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_MASK 0x08 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_ON 0x08 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_MASK 0x10 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_ON 0x10 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_MASK 0x20 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_ON 0x20 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_MASK 0x40 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_OFF 0x00 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_ON 0x40 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_MASK 0x80 |
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_OFF 0x00 |
DIGI IO SHT_VDD_EN register setting.
Specified setting for SHT_VDD_EN register of DIGI IO Click driver.
#define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_ON 0x80 |