digiio  2.1.0.0
digiio.h
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2 ** Copyright (C) 2020 MikroElektronika d.o.o.
3 ** Contact: https://www.mikroe.com/contact
4 **
5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
6 ** of this software and associated documentation files (the "Software"), to deal
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22 
28 #ifndef DIGIIO_H
29 #define DIGIIO_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
39 #ifdef PREINIT_SUPPORTED
40 #include "preinit.h"
41 #endif
42 
43 #ifdef MikroCCoreVersion
44  #if MikroCCoreVersion >= 1
45  #include "delays.h"
46  #endif
47 #endif
48 
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_spi_master.h"
52 #include "spi_specifics.h"
53 
74 #define DIGIIO_REG_SET_OUT 0x00
75 #define DIGIIO_REG_SET_LED 0x01
76 #define DIGIIO_REG_DOI_LEVEL 0x02
77 #define DIGIIO_REG_INTERRUPT 0x03
78 #define DIGIIO_REG_OVR_LD_CH_F 0x04
79 #define DIGIIO_REG_OPN_WIR_CH_F 0x05
80 #define DIGIIO_REG_SHT_VDD_CH_F 0x06
81 #define DIGIIO_REG_GLOBAL_ERR 0x07
82 #define DIGIIO_REG_OPN_WR_EN 0x08
83 #define DIGIIO_REG_SHT_VDD_EN 0x09
84 #define DIGIIO_REG_CONFIG_1 0x0A
85 #define DIGIIO_REG_CONFIG_2 0x0B
86 #define DIGIIO_REG_CONFIG_DI 0x0C
87 #define DIGIIO_REG_CONFIG_DO 0x0D
88 #define DIGIIO_REG_CURR_LIM 0x0E
89 #define DIGIIO_REG_MASK 0x0F
90  // digiio_reg
92 
107 #define DIGIIO_SET_OUT_SET_DI4_OUTPUT 0x00
108 #define DIGIIO_SET_OUT_SET_DI4_INPUT 0x80
109 #define DIGIIO_SET_OUT_SET_DI4_MASK 0x80
110 #define DIGIIO_SET_OUT_SET_DI3_OUTPUT 0x00
111 #define DIGIIO_SET_OUT_SET_DI3_INPUT 0x40
112 #define DIGIIO_SET_OUT_SET_DI3_MASK 0x40
113 #define DIGIIO_SET_OUT_SET_DI2_OUTPUT 0x00
114 #define DIGIIO_SET_OUT_SET_DI2_INPUT 0x20
115 #define DIGIIO_SET_OUT_SET_DI2_MASK 0x20
116 #define DIGIIO_SET_OUT_SET_DI1_OUTPUT 0x00
117 #define DIGIIO_SET_OUT_SET_DI1_INPUT 0x10
118 #define DIGIIO_SET_OUT_SET_DI1_MASK 0x10
119 #define DIGIIO_SET_OUT_HIGH_O4_LOW 0x00
120 #define DIGIIO_SET_OUT_HIGH_O4_HIGH 0x08
121 #define DIGIIO_SET_OUT_HIGH_O4_MASK 0x08
122 #define DIGIIO_SET_OUT_HIGH_O3_LOW 0x00
123 #define DIGIIO_SET_OUT_HIGH_O3_HIGH 0x04
124 #define DIGIIO_SET_OUT_HIGH_O3_MASK 0x04
125 #define DIGIIO_SET_OUT_HIGH_O2_LOW 0x00
126 #define DIGIIO_SET_OUT_HIGH_O2_HIGH 0x02
127 #define DIGIIO_SET_OUT_HIGH_O2_MASK 0x02
128 #define DIGIIO_SET_OUT_HIGH_O1_LOW 0x00
129 #define DIGIIO_SET_OUT_HIGH_O1_HIGH 0x01
130 #define DIGIIO_SET_OUT_HIGH_O1_MASK 0x01
131 
136 #define DIGIIO_SET_LED_SLED4_OFF 0x00
137 #define DIGIIO_SET_LED_SLED4_ON 0x80
138 #define DIGIIO_SET_LED_SLED4_MASK 0x80
139 #define DIGIIO_SET_LED_SLED3_OFF 0x00
140 #define DIGIIO_SET_LED_SLED3_ON 0x40
141 #define DIGIIO_SET_LED_SLED3_MASK 0x40
142 #define DIGIIO_SET_LED_SLED2_OFF 0x00
143 #define DIGIIO_SET_LED_SLED2_ON 0x20
144 #define DIGIIO_SET_LED_SLED2_MASK 0x20
145 #define DIGIIO_SET_LED_SLED1_OFF 0x00
146 #define DIGIIO_SET_LED_SLED1_ON 0x10
147 #define DIGIIO_SET_LED_SLED1_MASK 0x10
148 #define DIGIIO_SET_LED_FLED4_OFF 0x00
149 #define DIGIIO_SET_LED_FLED4_ON 0x08
150 #define DIGIIO_SET_LED_FLED4_MASK 0x08
151 #define DIGIIO_SET_LED_FLED3_OFF 0x00
152 #define DIGIIO_SET_LED_FLED3_ON 0x04
153 #define DIGIIO_SET_LED_FLED3_MASK 0x04
154 #define DIGIIO_SET_LED_FLED2_OFF 0x00
155 #define DIGIIO_SET_LED_FLED2_ON 0x02
156 #define DIGIIO_SET_LED_FLED2_MASK 0x02
157 #define DIGIIO_SET_LED_FLED1_OFF 0x00
158 #define DIGIIO_SET_LED_FLED1_ON 0x01
159 #define DIGIIO_SET_LED_FLED1_MASK 0x01
160 
165 #define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F4 0x80
166 #define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F3 0x40
167 #define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F2 0x20
168 #define DIGIIO_DOI_LEVEL_SAFE_DEMAG_F1 0x10
169 #define DIGIIO_DOI_LEVEL_DOI4 0x08
170 #define DIGIIO_DOI_LEVEL_DOI3 0x04
171 #define DIGIIO_DOI_LEVEL_DOI2 0x02
172 #define DIGIIO_DOI_LEVEL_DOI1 0x01
173 
178 #define DIGIIO_INTERRUPT_COMM_ERR 0x80
179 #define DIGIIO_INTERRUPT_SUPPLY_ERR 0x40
180 #define DIGIIO_INTERRUPT_DEMAG_FAULT 0x20
181 #define DIGIIO_INTERRUPT_SHT_VDD_FAULT 0x10
182 #define DIGIIO_INTERRUPT_ABOVE_VDD_FAULT 0x08
183 #define DIGIIO_INTERRUPT_OW_OFF_FAULT 0x04
184 #define DIGIIO_INTERRUPT_CURR_LIM 0x02
185 #define DIGIIO_INTERRUPT_OVER_LD_FAULT 0x01
186 
191 #define DIGIIO_OVR_LD_CH_F_CL4 0x80
192 #define DIGIIO_OVR_LD_CH_F_CL3 0x40
193 #define DIGIIO_OVR_LD_CH_F_CL2 0x20
194 #define DIGIIO_OVR_LD_CH_F_CL1 0x10
195 #define DIGIIO_OVR_LD_CH_F_OVL4 0x08
196 #define DIGIIO_OVR_LD_CH_F_OVL3 0x04
197 #define DIGIIO_OVR_LD_CH_F_OVL2 0x02
198 #define DIGIIO_OVR_LD_CH_F_OVL1 0x01
199 
204 #define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD4 0x80
205 #define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD3 0x40
206 #define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD2 0x20
207 #define DIGIIO_OPN_WIR_CH_F_ABOVE_VDD1 0x10
208 #define DIGIIO_OPN_WIR_CH_F_OW_OFF4 0x08
209 #define DIGIIO_OPN_WIR_CH_F_OW_OFF3 0x04
210 #define DIGIIO_OPN_WIR_CH_F_OW_OFF2 0x02
211 #define DIGIIO_OPN_WIR_CH_F_OW_OFF1 0x01
212 
217 #define DIGIIO_SHT_VDD_CH_F_VDD_OV4 0x80
218 #define DIGIIO_SHT_VDD_CH_F_VDD_OV3 0x40
219 #define DIGIIO_SHT_VDD_CH_F_VDD_OV2 0x20
220 #define DIGIIO_SHT_VDD_CH_F_VDD_OV1 0x10
221 #define DIGIIO_SHT_VDD_CH_F_SH_VDD4 0x08
222 #define DIGIIO_SHT_VDD_CH_F_SH_VDD3 0x04
223 #define DIGIIO_SHT_VDD_CH_F_SH_VDD2 0x02
224 #define DIGIIO_SHT_VDD_CH_F_SH_VDD1 0x01
225 
230 #define DIGIIO_GLOBAL_ERR_W_DOG_ERR 0x80
231 #define DIGIIO_GLOBAL_ERR_LOSS_GND 0x40
232 #define DIGIIO_GLOBAL_ERR_THRM_SHUTD 0x20
233 #define DIGIIO_GLOBAL_ERR_VDD_UVLO 0x10
234 #define DIGIIO_GLOBAL_ERR_VDD_WARN 0x08
235 #define DIGIIO_GLOBAL_ERR_VDD_LOW 0x04
236 #define DIGIIO_GLOBAL_ERR_V5_UVLO 0x02
237 #define DIGIIO_GLOBAL_ERR_VINT_UV 0x01
238 
243 #define DIGIIO_OPN_WR_EN_G_DRV_EN4_OFF 0x00
244 #define DIGIIO_OPN_WR_EN_G_DRV_EN4_ON 0x80
245 #define DIGIIO_OPN_WR_EN_G_DRV_EN4_MASK 0x80
246 #define DIGIIO_OPN_WR_EN_G_DRV_EN3_OFF 0x00
247 #define DIGIIO_OPN_WR_EN_G_DRV_EN3_ON 0x40
248 #define DIGIIO_OPN_WR_EN_G_DRV_EN3_MASK 0x40
249 #define DIGIIO_OPN_WR_EN_G_DRV_EN2_OFF 0x00
250 #define DIGIIO_OPN_WR_EN_G_DRV_EN2_ON 0x20
251 #define DIGIIO_OPN_WR_EN_G_DRV_EN2_MASK 0x20
252 #define DIGIIO_OPN_WR_EN_G_DRV_EN1_OFF 0x00
253 #define DIGIIO_OPN_WR_EN_G_DRV_EN1_ON 0x10
254 #define DIGIIO_OPN_WR_EN_G_DRV_EN1_MASK 0x10
255 #define DIGIIO_OPN_WR_EN_OW_OFF_EN4_OFF 0x00
256 #define DIGIIO_OPN_WR_EN_OW_OFF_EN4_ON 0x08
257 #define DIGIIO_OPN_WR_EN_OW_OFF_EN4_MASK 0x08
258 #define DIGIIO_OPN_WR_EN_OW_OFF_EN3_OFF 0x00
259 #define DIGIIO_OPN_WR_EN_OW_OFF_EN3_ON 0x04
260 #define DIGIIO_OPN_WR_EN_OW_OFF_EN3_MASK 0x04
261 #define DIGIIO_OPN_WR_EN_OW_OFF_EN2_OFF 0x00
262 #define DIGIIO_OPN_WR_EN_OW_OFF_EN2_ON 0x02
263 #define DIGIIO_OPN_WR_EN_OW_OFF_EN2_MASK 0x02
264 #define DIGIIO_OPN_WR_EN_OW_OFF_EN1_OFF 0x00
265 #define DIGIIO_OPN_WR_EN_OW_OFF_EN1_ON 0x01
266 #define DIGIIO_OPN_WR_EN_OW_OFF_EN1_MASK 0x01
267 
272 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_OFF 0x00
273 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_ON 0x80
274 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN4_MASK 0x80
275 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_OFF 0x00
276 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_ON 0x40
277 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN3_MASK 0x40
278 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_OFF 0x00
279 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_ON 0x20
280 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN2_MASK 0x20
281 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_OFF 0x00
282 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_ON 0x10
283 #define DIGIIO_SHT_VDD_EN_VDD_OV_EN1_MASK 0x10
284 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_OFF 0x00
285 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_ON 0x08
286 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN4_MASK 0x08
287 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_OFF 0x00
288 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_ON 0x04
289 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN3_MASK 0x04
290 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_OFF 0x00
291 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_ON 0x02
292 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN2_MASK 0x02
293 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_OFF 0x00
294 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_ON 0x01
295 #define DIGIIO_SHT_VDD_EN_SH_VDD_EN1_MASK 0x01
296 
301 #define DIGIIO_CONFIG_1_LED_CURR_LIM_OFF 0x00
302 #define DIGIIO_CONFIG_1_LED_CURR_LIM_ON 0x80
303 #define DIGIIO_CONFIG_1_LED_CURR_LIM_MASK 0x80
304 #define DIGIIO_CONFIG_1_FLATCH_EN_OFF 0x00
305 #define DIGIIO_CONFIG_1_FLATCH_EN_ON 0x40
306 #define DIGIIO_CONFIG_1_FLATCH_EN_MASK 0x40
307 #define DIGIIO_CONFIG_1_FILTER_LONG_4_MS 0x00
308 #define DIGIIO_CONFIG_1_FILTER_LONG_8_MS 0x20
309 #define DIGIIO_CONFIG_1_FILTER_LONG_MASK 0x20
310 #define DIGIIO_CONFIG_1_FFILTER_EN_OFF 0x00
311 #define DIGIIO_CONFIG_1_FFILTER_EN_ON 0x10
312 #define DIGIIO_CONFIG_1_FFILTER_EN_MASK 0x10
313 #define DIGIIO_CONFIG_1_FLED_STRETCH_OFF 0x00
314 #define DIGIIO_CONFIG_1_FLED_STRETCH_1_S 0x04
315 #define DIGIIO_CONFIG_1_FLED_STRETCH_2_S 0x08
316 #define DIGIIO_CONFIG_1_FLED_STRETCH_3_S 0x0C
317 #define DIGIIO_CONFIG_1_FLED_STRETCH_MASK 0x0C
318 #define DIGIIO_CONFIG_1_SLED_SET_DOI 0x00
319 #define DIGIIO_CONFIG_1_SLED_SET_REG 0x02
320 #define DIGIIO_CONFIG_1_SLED_SET_MASK 0x02
321 #define DIGIIO_CONFIG_1_FLED_SET_DOI 0x00
322 #define DIGIIO_CONFIG_1_FLED_SET_REG 0x01
323 #define DIGIIO_CONFIG_1_FLED_SET_MASK 0x01
324 
329 #define DIGIIO_CONFIG_2_WDTO_OFF 0x00
330 #define DIGIIO_CONFIG_2_WDTO_200_MS 0x40
331 #define DIGIIO_CONFIG_2_WDTO_600_MS 0x80
332 #define DIGIIO_CONFIG_2_WDTO_1200_MS 0xC0
333 #define DIGIIO_CONFIG_2_WDTO_MASK 0xC0
334 #define DIGIIO_CONFIG_2_OW_OFF_C_S_60_UA 0x00
335 #define DIGIIO_CONFIG_2_OW_OFF_C_S_100_UA 0x10
336 #define DIGIIO_CONFIG_2_OW_OFF_C_S_300_UA 0x20
337 #define DIGIIO_CONFIG_2_OW_OFF_C_S_600_UA 0x30
338 #define DIGIIO_CONFIG_2_OW_OFF_C_S_MASK 0x30
339 #define DIGIIO_CONFIG_2_SHT_VDD_THR_9_V 0x00
340 #define DIGIIO_CONFIG_2_SHT_VDD_THR_10_V 0x04
341 #define DIGIIO_CONFIG_2_SHT_VDD_THR_12_V 0x08
342 #define DIGIIO_CONFIG_2_SHT_VDD_THR_14_V 0x0C
343 #define DIGIIO_CONFIG_2_SHT_VDD_THR_MASK 0x0C
344 #define DIGIIO_CONFIG_2_SYNCH_WD_EN_OFF 0x00
345 #define DIGIIO_CONFIG_2_SYNCH_WD_EN_ON 0x02
346 #define DIGIIO_CONFIG_2_SYNCH_WD_EN_MASK 0x02
347 #define DIGIIO_CONFIG_2_VDD_ON_THR_OFF 0x00
348 #define DIGIIO_CONFIG_2_VDD_ON_THR_ON 0x01
349 #define DIGIIO_CONFIG_2_VDD_ON_THR_MASK 0x01
350 
355 #define DIGIIO_CONFIG_DI_TYP_2_DI_TYPE_1_3 0x00
356 #define DIGIIO_CONFIG_DI_TYP_2_DI_TYPE_2 0x80
357 #define DIGIIO_CONFIG_DI_TYP_2_DI_MASK 0x80
358 #define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_OFF 0x00
359 #define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_ON 0x20
360 #define DIGIIO_CONFIG_DI_VDD_FAULT_DIS_MASK 0x20
361 #define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_DOI 0x00
362 #define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_VDDOK 0x10
363 #define DIGIIO_CONFIG_DI_VDD_FAULT_SEL_MASK 0x10
364 #define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_OFF 0x00
365 #define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_ON 0x08
366 #define DIGIIO_CONFIG_DI_ABOVE_VDD_PROT_EN_MASK 0x08
367 #define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_OFF 0x00
368 #define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_ON 0x04
369 #define DIGIIO_CONFIG_DI_OVL_STRETCH_EN_MASK 0x04
370 #define DIGIIO_CONFIG_DI_OVL_BLANK_OFF 0x00
371 #define DIGIIO_CONFIG_DI_OVL_BLANK_8_MS 0x01
372 #define DIGIIO_CONFIG_DI_OVL_BLANK_50_MS 0x02
373 #define DIGIIO_CONFIG_DI_OVL_BLANK_300_MS 0x03
374 #define DIGIIO_CONFIG_DI_OVL_BLANK_MASK 0x03
375 
380 #define DIGIIO_CONFIG_DO_MODE4_HIGH_SIDE 0x00
381 #define DIGIIO_CONFIG_DO_MODE4_HIGH_SIDE_2X 0x40
382 #define DIGIIO_CONFIG_DO_MODE4_ACTIVE_CLAMP_PP 0x80
383 #define DIGIIO_CONFIG_DO_MODE4_SIMPLE_PP 0xC0
384 #define DIGIIO_CONFIG_DO_MODE4_MASK 0xC0
385 #define DIGIIO_CONFIG_DO_MODE3_HIGH_SIDE 0x00
386 #define DIGIIO_CONFIG_DO_MODE3_HIGH_SIDE_2X 0x10
387 #define DIGIIO_CONFIG_DO_MODE3_ACTIVE_CLAMP_PP 0x20
388 #define DIGIIO_CONFIG_DO_MODE3_SIMPLE_PP 0x30
389 #define DIGIIO_CONFIG_DO_MODE3_MASK 0x30
390 #define DIGIIO_CONFIG_DO_MODE2_HIGH_SIDE 0x00
391 #define DIGIIO_CONFIG_DO_MODE2_HIGH_SIDE_2X 0x04
392 #define DIGIIO_CONFIG_DO_MODE2_ACTIVE_CLAMP_PP 0x08
393 #define DIGIIO_CONFIG_DO_MODE2_SIMPLE_PP 0x0C
394 #define DIGIIO_CONFIG_DO_MODE2_MASK 0x0C
395 #define DIGIIO_CONFIG_DO_MODE1_HIGH_SIDE 0x00
396 #define DIGIIO_CONFIG_DO_MODE1_HIGH_SIDE_2X 0x01
397 #define DIGIIO_CONFIG_DO_MODE1_ACTIVE_CLAMP_PP 0x02
398 #define DIGIIO_CONFIG_DO_MODE1_SIMPLE_PP 0x03
399 #define DIGIIO_CONFIG_DO_MODE1_MASK 0x03
400 
405 #define DIGIIO_CURR_LIM_CL4_600_MA 0x00
406 #define DIGIIO_CURR_LIM_CL4_130_MA 0x40
407 #define DIGIIO_CURR_LIM_CL4_300_MA 0x80
408 #define DIGIIO_CURR_LIM_CL4_1200_MA 0xC0
409 #define DIGIIO_CURR_LIM_CL4_MASK 0xC0
410 #define DIGIIO_CURR_LIM_CL3_600_MA 0x00
411 #define DIGIIO_CURR_LIM_CL3_130_MA 0x10
412 #define DIGIIO_CURR_LIM_CL3_300_MA 0x20
413 #define DIGIIO_CURR_LIM_CL3_1200_MA 0x30
414 #define DIGIIO_CURR_LIM_CL3_MASK 0x30
415 #define DIGIIO_CURR_LIM_CL2_600_MA 0x00
416 #define DIGIIO_CURR_LIM_CL2_130_MA 0x04
417 #define DIGIIO_CURR_LIM_CL2_300_MA 0x08
418 #define DIGIIO_CURR_LIM_CL2_1200_MA 0x0C
419 #define DIGIIO_CURR_LIM_CL2_MASK 0x0C
420 #define DIGIIO_CURR_LIM_CL1_600_MA 0x00
421 #define DIGIIO_CURR_LIM_CL1_130_MA 0x01
422 #define DIGIIO_CURR_LIM_CL1_300_MA 0x02
423 #define DIGIIO_CURR_LIM_CL1_1200_MA 0x03
424 #define DIGIIO_CURR_LIM_CL1_MASK 0x03
425 
430 #define DIGIIO_MASK_COMM_ERR_M 0x80
431 #define DIGIIO_MASK_SUPPLY_ERR_M 0x40
432 #define DIGIIO_MASK_VDD_OK_M 0x20
433 #define DIGIIO_MASK_SHT_VDD_M 0x10
434 #define DIGIIO_MASK_ABOVE_VDD_M 0x08
435 #define DIGIIO_MASK_OW_OFF_M 0x04
436 #define DIGIIO_MASK_CURR_LIM_M 0x02
437 #define DIGIIO_MASK_OVER_LD_M 0x01
438 
443 #define DIGIIO_CRC_ENABLED 0x01
444 #define DIGIIO_CRC_DISABLED 0x00
445 
450 #define DIGIIO_DEVICE_ADDRESS_0 0x00
451 #define DIGIIO_DEVICE_ADDRESS_1 0x40
452 #define DIGIIO_DEVICE_ADDRESS_2 0x80
453 #define DIGIIO_DEVICE_ADDRESS_3 0xC0
454 
463 #define DIGIIO_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
464 #define DIGIIO_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
465  // digiio_set
467 
482 #define DIGIIO_MAP_MIKROBUS( cfg, mikrobus ) \
483  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
484  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
485  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
486  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
487  cfg.rdy = MIKROBUS( mikrobus, MIKROBUS_AN ); \
488  cfg.en = MIKROBUS( mikrobus, MIKROBUS_RST ); \
489  cfg.syn = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
490  cfg.flt = MIKROBUS( mikrobus, MIKROBUS_INT )
491  // digiio_map // digiio
494 
499 typedef struct
500 {
501  // Output pins
502  digital_out_t en;
503  digital_out_t syn;
505  // Input pins
506  digital_in_t rdy;
507  digital_in_t flt;
509  // Modules
510  spi_master_t spi;
512  pin_name_t chip_select;
514  uint8_t device_address;
515  uint8_t crc_en;
517 } digiio_t;
518 
523 typedef struct
524 {
525  // Communication gpio pins
526  pin_name_t miso;
527  pin_name_t mosi;
528  pin_name_t sck;
529  pin_name_t cs;
531  // Additional gpio pins
532  pin_name_t rdy;
533  pin_name_t en;
534  pin_name_t syn;
535  pin_name_t flt;
537  // static variable
538  uint32_t spi_speed;
539  spi_master_mode_t spi_mode;
540  spi_master_chip_select_polarity_t cs_polarity;
542 } digiio_cfg_t;
543 
548 typedef enum
549 {
551  DIGIIO_ERROR = -1
552 
554 
571 
585 err_t digiio_init ( digiio_t *ctx, digiio_cfg_t *cfg );
586 
600 
610 void digiio_set_address ( digiio_t *ctx, uint8_t device_address );
611 
624 err_t digiio_write_reg ( digiio_t *ctx, uint8_t reg, uint8_t data_in );
625 
638 err_t digiio_read_reg ( digiio_t *ctx, uint8_t reg, uint8_t *data_out );
639 
649 
659 
668 void digiio_sync_io ( digiio_t *ctx );
669 
679 void digiio_set_sync_pin ( digiio_t *ctx, uint8_t state );
680 
690 
700 
701 #ifdef __cplusplus
702 }
703 #endif
704 #endif // DIGIIO_H
705  // digiio
707 
708 // ------------------------------------------------------------------------ END
digiio_t::syn
digital_out_t syn
Definition: digiio.h:503
DIGIIO_ERROR
@ DIGIIO_ERROR
Definition: digiio.h:551
digiio_get_ready_pin
uint8_t digiio_get_ready_pin(digiio_t *ctx)
DIGI IO get ready pin function.
digiio_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: digiio.h:540
digiio_enable_output
void digiio_enable_output(digiio_t *ctx)
DIGI IO enable output function.
digiio_cfg_t
DIGI IO Click configuration object.
Definition: digiio.h:524
digiio_t::en
digital_out_t en
Definition: digiio.h:502
digiio_cfg_t::mosi
pin_name_t mosi
Definition: digiio.h:527
digiio_cfg_t::sck
pin_name_t sck
Definition: digiio.h:528
spi_specifics.h
This file contains SPI specific macros, functions, etc.
digiio_cfg_t::syn
pin_name_t syn
Definition: digiio.h:534
digiio_t::flt
digital_in_t flt
Definition: digiio.h:507
digiio_cfg_t::flt
pin_name_t flt
Definition: digiio.h:535
digiio_cfg_t::spi_speed
uint32_t spi_speed
Definition: digiio.h:538
digiio_set_address
void digiio_set_address(digiio_t *ctx, uint8_t device_address)
DIGI IO set address function.
digiio_cfg_t::rdy
pin_name_t rdy
Definition: digiio.h:532
DIGIIO_OK
@ DIGIIO_OK
Definition: digiio.h:550
digiio_init
err_t digiio_init(digiio_t *ctx, digiio_cfg_t *cfg)
DIGI IO initialization function.
digiio_disable_output
void digiio_disable_output(digiio_t *ctx)
DIGI IO disable output function.
digiio_cfg_t::en
pin_name_t en
Definition: digiio.h:533
digiio_t::spi
spi_master_t spi
Definition: digiio.h:510
digiio_cfg_t::miso
pin_name_t miso
Definition: digiio.h:526
digiio_t::device_address
uint8_t device_address
Definition: digiio.h:514
digiio_t::crc_en
uint8_t crc_en
Definition: digiio.h:515
digiio_write_reg
err_t digiio_write_reg(digiio_t *ctx, uint8_t reg, uint8_t data_in)
DIGI IO write reg function.
digiio_t
DIGI IO Click context object.
Definition: digiio.h:500
digiio_get_fault_pin
uint8_t digiio_get_fault_pin(digiio_t *ctx)
DIGI IO get fault pin function.
digiio_t::chip_select
pin_name_t chip_select
Definition: digiio.h:512
digiio_t::rdy
digital_in_t rdy
Definition: digiio.h:506
digiio_cfg_setup
void digiio_cfg_setup(digiio_cfg_t *cfg)
DIGI IO configuration object setup function.
digiio_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: digiio.h:539
digiio_set_sync_pin
void digiio_set_sync_pin(digiio_t *ctx, uint8_t state)
DIGI IO set sync pin function.
digiio_read_reg
err_t digiio_read_reg(digiio_t *ctx, uint8_t reg, uint8_t *data_out)
DIGI IO read reg function.
digiio_return_value_t
digiio_return_value_t
DIGI IO Click return value data.
Definition: digiio.h:549
digiio_cfg_t::cs
pin_name_t cs
Definition: digiio.h:529
digiio_default_cfg
err_t digiio_default_cfg(digiio_t *ctx)
DIGI IO default configuration function.
digiio_sync_io
void digiio_sync_io(digiio_t *ctx)
DIGI IO sync io function.